Pin Diagram of 8086

 Pin Diagram of 8086

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       Figure shows 40 pin lay-out for 8086 Microprocessor. The designers of 8086 were able to reduce number of pins on the IC (Integrated circuit) of 8086 to 40, because they have used a concept called as "Time Multiplexing" for designing the IC. Time multiplexing means we can use same pin/pins of 8086 to perform two different functions depending upon time.

    The 8086 Microprocessor can work in two operating modes i.e. Minimum and Maximum. Functions of pin number 24 to 31 are different in minimum and maximum mode. The functions of remaining pins are same for minimum and maximum mode.

 A. Pin definitions common to Minimum and Maximum Mode

 1. Address/Data Bus (AD0 to AD15): These are time multiplexed address and data lines of 8086. These 16 lines are used to carry address of memory or I/O devices during T1 state of machine cycle. The same lines are used to carry data during T2, T3 and T4 states.

 2. Address/ status lines (A16/S3 to A19/S6): These are multiplexed address/status lines of 8086. During T1 these 4 lines carry higher address of memory or I/O device. During T2 to T4 these lines carry status information. Status bit S5 indicates the status of IF flag and S6 is always zero. Status bits S3 and S4 are used to indicate with which segment 8086 is currently working as per following table

 

S4    S3    Segment Accessed

0        0     Extra segment

0        1     Stack segment

1        0     Code segment  

1        1     Data segment

  3. Bus High Enable/status (BHE/S7): This is multiplexed enable/status signal. BHE is outputted by 8086 to enable data transfer on D8 to D15 data bus. Status bit S7 always a logic 1.

 4. Non-maskable interrupt (NMI): This is non maskable interrupt input of 8086. Whenever this pin is activated by external signal the operation of Microprocessor is interrupted. The signal on this pin cannot be disabled by 8086. This pin is used to interrupt the operation of 8086 in certain critical conditions and in case of power failure.

5. Interrupt (INTR): This is maskable interrupt of 8086. This interrupt can be enabled or disabled by using interrupt flag (IF) in flag register. Two instructions STI and CLI are used to enable and disable this input pin.

 6. Clock (CLK): This input pin is used to provide required clock signal for the operation of 8086 Microprocessor. 8086 is not capable of generating required clock frequency for its operation. Therefore, it is supplied using external device such as 8284 clock generators.

7. Reset: This is RESET input of 8086 Microprocessor. Whenever 8086 is reset it stops executing current program and fetches the first instruction from memory address.

8. Ready: This input pin is used by 8086 to perform data transfer with slow memory or I/O devices. Using this pin, a slow memory or I/O device informs 8086 whether it is ready to perform data transfer or not.

9. TEST: This input signal is checked by 8086 when it executes "Wait" instruction. It is generally connected to numeric data processor (Math Coprocessor) 8087. Using this input pin 8086 confirms whether 8087 has completed the operation or not.

10. MN/MX: This input pin determines the mode of operation for 8086 Microprocessor. When this pin is connected to Vcc (High) then 8086 operate in minimum mode. When the same pin is connected to ground (Low) 8086 operate in maximum mode.

 1. Read (RD): This control signal is outputted by 8086 in T2 state to read data from memory or I/O device.

 B. Pin definitions for Minimum Mode

 1. Interrupt Acknowledge (INTA): This signal is outputted by 8086 in response to input signal on     INTR input pin. If this output pin is made low by 8086 then it means that 8086 has accepted interrupt on INTR input and is ready to perform the work requested by I/O device.

2. Address latch enable (ALE): This control signal is outputted by 8086 in T1 state to enable           address latches connected to address bus. The address latches are required to demultiplex (separate) address and data lines of 8086.

 3. Data Enable (DEN): This control signal is outputted by 8086 in T2 state to enable bidirectional buffers connected to data bus of 8086.

4. Data Transmit/ Receive (DT/R): This control signal is outputted by 8086 in T1 state to tell the direction of data flow to bidirectional buffers. If this pin is made high by 8086 then it is performing write (Transmit) operation. If this pin is made low by 8086 then it is performing read (Receive) operation.

5. M/TO: This control signal is outputted by 8086 in T1 state to distinguish between memory cycle and I/O cycle. If this pin is made high by 8086 then it is working with memory. If this pin is made low by 8086 then it is working with I/O devices.

 6. Write (WR): This control signal is outputted by 8086 in T2 state to write data into memory or V/O device.

 7. HOLD: This input pin of 8086 is used by DMA (Direct memory access) controller to request the access of system bus (Address, Data and Control) for transferring data directly to memory. When this input pin to 8086 is made high by DMA controller 8086 completes current instruction and then releases system bus to DMA controller.

 8. HLDA: This is an output pin of 8086. It is made high by 8086 in response to the HOLD request from DMA controller. This is an acknowledgement from 8086 to DMA controller. When 8086 receives DMA request on HOLD pin, it releases system bus to the DMA controller and make HLDA high to inform DMA controller that it has released the system bus.

 C. Pin definitions for Maximum Mode

1.      S0, S1, S2 (Status Bits): These are the status bit signals connected to 8288 bus controller. By decoding these 3 bits 8288 understands what type of instruction 8086 is executing. Then 8288 bus controller generates required control signals for memory and I/O devices. These 3 bits are decoded as follows

S2   S1   S0               Types of operation

0    0       0                 Interrupt Acknowledge

0    0       1                 Read I/O port

0    1       0                 Write I/O port

0     1       1                 Halt

      1    0       0                 Instruction fetch

1    0       1                 Read memory

1    1       1                 Write memory

1    1       0                  Passive

 

2. QS0 and QS1 (Queue status): These two bits are used by 8086 to show the status of instruction queue. These 2 bits are often used by 8087 coprocessor to monitor the internal queue of 8086. These 2 bits are decoded as follows

 QS1   QS0

0          0          : No operation

0          1          : The first byte of current instruction is being executed

1          1          : The subsequent byte of current instruction is being executed.

1          0          : Queue is empty

 3. LOCK: This pin is activated by 8086 when an instruction with LOCK prefix is executed. When instruction with LOCK prefix is executed by Microprocessor, the access of system bus (Address, Data and Control Bus) is not given to another processor (8087) connected in the system.

 4. RQ/GTO and RQ/GTI: These are bidirectional request/grant pins used in maximum mode for DMA (Direct memory access) operations. These pins are bidirectional means using the same pin both DMA request and DMA grant signals are activated. The priority of RQ/GTO is higher than RQ/GTI pin.